DK-DEV-5SGXEA7N【PDF 77/527 页】KIT DEV STRATIX V FPGA 5SGXEA7

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SV51005

2014.01.10

Clock Sources Per Quadrant

4-7

Figure 4-8: PCLK Networks for Stratix V E E9 and EB Devices, and Stratix V GX A9, AB, BB, and B9 Devices

This figure represents the top view of the silicon die that corresponds to a reverse view of the device package.

Vertical

PCLK[0..25]

Horizontal

PCLK[0..20]

Horizontal

Vertical

PCLK[113..137]

Horizontal

PCLK[146..167]

Horizontal

PCLK[21..42]

Horizontal

PCLK[43..64]

Horizontal

PCLK[65..83]

Vertical

PCLK[26..51]

Q1

Q4

Q2

Q3

PCLK[125..146]

Horizontal

PCLK[103..124]

Horizontal

PCLK[84..102]

Vertical

PCLK[88..112]

Clock Sources Per Quadrant

The Stratix V devices provide 33 section clock (SCLK) networks in each spine clock per quadrant. The SCLK

networks can drive six row clocks in each logic array block (LAB) row, nine column I/O clocks, and two

core reference clocks. The SCLKs are the clock resources to the core functional blocks, PLLs, and I/O interfaces

of the device.

A spine clock is another layer of routing between the GCLK, RCLK, and PCLK networks before each clock

is connected to the clock routing for each LAB row. The settings for spine clocks are transparent. The

Quartus II software automatically routes the spine clock based on the GCLK, RCLK, and PCLK networks.

The following figure shows SCLKs driven by the GCLK, RCLK, PCLK, or the PLL feedback clock networks

in each spine clock per quadrant. The GCLK, RCLK, PCLK, and PLL feedback clocks share the same routing

to the SCLKs. To ensure successful design fitting in the Quartus II software, the total number of clock

resources must not exceed the SCLK limits in each region.

Clock Networks and PLLs in Stratix V Devices

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